First from Abtruse Goose. I know I've thought about my dream house...grand vaulted ceilings, stone walls, fiber to the wall and personalized access via tamperproof RF badges....
Second from Brown Sharpie. I know that GWU is going to look like that on Monday of next week.
Monday, May 11, 2009
Saturday, May 09, 2009
Finished
I'm finished with school. Finally.
Well, kinda finished. At least for a bit.
I have finished my last semester of my undergraduate engineering studies at GWU [1]. I came out of this spring semester with an butchered senior thesis project, but also with my second asic design. While my senior thesis was an fpga based SoC, doing encryption and communication; my asic is actually a microprocessor. It is a 8 bit CISC electric brain, using an acummulator based model. I have plans to take this to fabrication on the June MOSIS MEP run on AMI 0.5um process. Not only has this been implemented but simulated with a dsp system. My post fabrication verification plans including using an Fpga to emulate the block ram and handle the dac/adc parts.
The ASIC work is actually pretty exciting for me, since I don't do anything at all like this at my job. I'm really driving this myself with the support of a professor. I'm thinking about it as though I was working in the Eda industry, it's like free on the job style training. I even get to self pace my work since it's not for a course. I'll have the signoff for fab in late June, which will give me 2-3 months to have designed, implemented and tested the verification platform. One thing to keep in mind is that the processor was built using a RTL to GDSII flow, so it would not be difficult to implement the uP on an fpga too.
I have several busy evenings because of this project, but it will keep me sharp on my engineering skillset while I'm working an IT Support gig full time. I guess what it really is, in reality, is how much more free my brain is with the spectre of other coursework or senior design over my head.
It's a beautiful day. No more writing, time to play.
Seraph
[1] I still have a professional ethics philosophy course to finish. meh.
Well, kinda finished. At least for a bit.
I have finished my last semester of my undergraduate engineering studies at GWU [1]. I came out of this spring semester with an butchered senior thesis project, but also with my second asic design. While my senior thesis was an fpga based SoC, doing encryption and communication; my asic is actually a microprocessor. It is a 8 bit CISC electric brain, using an acummulator based model. I have plans to take this to fabrication on the June MOSIS MEP run on AMI 0.5um process. Not only has this been implemented but simulated with a dsp system. My post fabrication verification plans including using an Fpga to emulate the block ram and handle the dac/adc parts.
The ASIC work is actually pretty exciting for me, since I don't do anything at all like this at my job. I'm really driving this myself with the support of a professor. I'm thinking about it as though I was working in the Eda industry, it's like free on the job style training. I even get to self pace my work since it's not for a course. I'll have the signoff for fab in late June, which will give me 2-3 months to have designed, implemented and tested the verification platform. One thing to keep in mind is that the processor was built using a RTL to GDSII flow, so it would not be difficult to implement the uP on an fpga too.
I have several busy evenings because of this project, but it will keep me sharp on my engineering skillset while I'm working an IT Support gig full time. I guess what it really is, in reality, is how much more free my brain is with the spectre of other coursework or senior design over my head.
It's a beautiful day. No more writing, time to play.
Seraph
[1] I still have a professional ethics philosophy course to finish. meh.
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